This is a simulation only lab: Design a synchronous counter that will count the following sequence. 0, 1, 4, 5, 8, 9, 12, 13 and then recycle. Implement your circuit using negative edge-triggered J-K Flip Flops (74LS76). The clock will be a 5V, 1Hz pulse signal. You will submit your design process in a neat and orderly (digital) manner. Construct and simulate the entire circuit in Multisim. Use the 4-channel oscilloscope to verify the count sequence. Beneath the o-scope use the waveforms to list the count sequence.